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description the A6217 is a single ic switching regulator that provides constant-current output to drive high-power leds. it integrates a high-side n-channel dmos switch for dc-to-dc step- down (buck) conversion. a true average current is output using a cycle-by-cycle, controlled on-time method. output current is user-selectable by an external current sense resistor. output voltage is automatically adjusted to drive various numbers of leds in a single string. this ensures the optimal system efficiency. led dimming is accomplished by a direct logic input pulse- width-modulation (pwm) signal at the enable pin. the device is provided in a 3 mm 3 mm wettable flank 10-pin dfn (suffix ej) or an 8-pin narrow soic (suffix lj), both with exposed pad for enhanced thermal dissipation. both packages are lead (pb) free, with 100% matte-tin leadframe plating. A6217-ds features and benefits ? aec-q100 qualified ? 6 to 48 v supply voltage ? true average o utput current control ? 3 a maximum output over operating temperature range (1.5 a for A6217-1) ? cycle-by-cycle current limit ? integrated mosfet switch ? enable / pwm dimming via direct logic input or power supply voltage ? internal control loop compensa tion ? undervoltage lockout (uvlo) and thermal shutdown protection ? low power shutdown (1 a typical) ? robust protection against: ? adjacent pin-to -pin short ? pin-to-gnd short ? component op en/short faults ? enhancements over a6213: ? dithering of switching frequen cy to reduce emi ? able to drive single white led from 18 v supply at 2.2 mhz ? smaller packag e option automotive-grade, constant-current pwm dimmable buck regulator led driver packages: not to scale A6217 and A6217-1 typical application circuit applications: automotive lighting ? daytime running lights ? front and rear fog lights ? turn/stop light s ? map light ? dimmable interior lights c1 r1 gnd vin v in (6 to 48 v) 1, 2 3 4 5 9,10 8 7 6 sw gnd vcc A6217 (ej) boot ton en cs c5 c4 d1 l1 led + led? rsense en enable/pwm dimming (100 hz to 2 khz) . . . pad 10-pin dfn with wettable flank (suffix ej) 8-pin soicn (suffix lj)
2 absolute maximum ratings characteristic symbol notes rating unit supply voltage v in C0.3 to 50 v bootstrap drive voltage v boot C0.3 to v in + 8 v switching voltage v sw C1.5 to v in + 0.3 v linear regulator terminal v cc vcc to gnd C0.3 to 7 v enable and ton voltage v en , v ton C0.3 to v in + 0.3 v current sense voltage v cs C0.3 to 7 v maximum junction temperature t j (max) 150 oc storage temperature t stg C55 to 150 oc selection guide part number maximum output current (a) package packing A6217kejtr-j 3 wettable flank 10-pin dfn with exposed thermal pad contact factory A6217kejtr-1-j 1.5 wettable flank 10-pin dfn with exposed thermal pad contact factory A6217kljtr-t 3 8-pin soicn with exposed thermal pad 3000 pieces per 13-in. reel A6217kljtr-1-t 1.5 8-pin soicn with exposed thermal pad 3000 pieces per 13-in. reel pinout diagrams terminal list table number name function ej lj 1, 2 1 vin supply voltage input terminals 3 2 ton regulator on-time setting resistor terminal; determines the switching frequency of the converter 4 3 en input for enable and pwm dimming; rated up to v in and logic-level compatible 5 4 cs drive output current sense feedback 6 5 vcc internal linear regulator output; add filter capacitor of 0.1 f from this pin to gnd 7 6 gnd ground terminal 8 7 boot dmos gate driver bootstrap terminal 9, 10 8 sw switched output terminals C C pad exposed pad for enhanced thermal dissipation; connect to gnd thermal characteristics*: may require derating at maximum conditions; see application section for optimization characteristic symbol test conditions* value unit package thermal resistance (junction to ambient) r ja dfn-10 (ej) package on 4-layer pcb based on jedec standard 45 oc/w soicn-8 (lj) package on 4-layer pcb based on jedec standard 35 oc/w package thermal resistance (junction to pad) r jp 2 oc/w *additional thermal information available on the allegro ? website. 10 9 8 7 6 sw sw boot pa d gnd vcc 1 2 3 4 5 vin vin to n en cs package ej pinouts sw boot gnd vcc vin ton en cs 1 2 3 4 8 7 6 5 pad package lj pinouts automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 functional block diagram + ? + ? 0.2 v boot cvcc cboot l1 d1 led string vcc shutdown vin v in c comp en ton r on cs gnd rsense sw on-time current generator on-time timer ic and driver control logic level shift gate drive uvlo v cc uvlo off-time timer v reg 5.3 v + ? buck switch current sense current limit off-time timer i lim thermal shutdown v cc uvlo pad average + ? v il = 0.4 v v ih = 1.8 v dithering (5%) ~v out automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 electrical characteristics: valid at v in = 12 v, t j = C40c to 125c, typical values at t j = 25c, unless otherwise noted characteristics symbol test conditions min. typ. max. unit input supply voltage v in 6 C 48 v v in undervoltage lockout threshold v uvlo v in increasing C 5.3 C v v in undervoltage lockout hysteresis v uvlo _ hys v in decreasing C 150 C mv vin pin supply current i in vcs = 0.5 v, en = high C 2.5 C ma vin pin standby current i insb v cs = 0.5 v, en = high to low, within 10 ms C 1 C ma vin pin shutdown current i insd en shorted to gnd C 1 10 a buck switch current limit threshold i swlim A6217 3.0 4.0 5.0 a A6217-1 1.9 2.2 2.7 a buck switch on-resistance r ds(on) v boot = v in + 4.3 v, t a = 25c, i sw = 1 a C 0.25 0.4 boot undervoltage lockout threshold v bootuv v boot to v sw increasing 2.7 3.5 4.3 v boot undervoltage lockout hysteresis v botuvhys v boot to v sw decreasing C 370 C mv switching minimum off-time t offmin v cs = 0 v C 110 150 ns switching minimum on-time t onmin C 75 100 ns selected on-time t on v in = 12 v, v out = 6 v, r on = 31.6 k 200 250 300 ns oscillator frequency dithering range f sw_dith r on = 31.6 k C 5 C % dithering modulation frequency f sw_mod r on = 31.6 k C 11 C khz regulation comparator and error amplifier load current sense regulation threshold [1] v csreg v cs decreasing, sw turns on 187.5 200 210 mv load current sense bias current i csbias v cs = 0.2 v, en = low C 0.9 C a internal linear regulator vcc regulated output v cc 0 ma < i cc < 5 ma, v in > 6 v 5.1 5.4 5.7 v vcc current limit [2] i cclim v cc = 0 v 5 20 C ma enable input logic high voltage v ih v en increasing 1.8 C C v logic low voltage v il v en decreasing C C 0.4 v en pin pull-down resistance r enpd v en = 5 v C 100 C k maximum pwm dimming off-time t pwml measured while en = low, during dimming control, and internal references are powered on (exceeding t pwml results in shutdown) 12 20 C ms thermal shutdown thermal shutdown threshold t sd C 165 C c thermal shutdown hysteresis t sdhys C 25 C c 1 in test mode, a ramp signal is applied at cs pin to determine the cs pin regulation threshold voltage. in actual application, the average cs pin voltage is regulated at v csreg regardless of ripple voltage. 2 the internal linear regulator is not designed to drive an external load automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 characteristic performance panel 1b. v in = 12 v panel 1c. v in = 18 v panel 1a. v in = 7 v figure 1: startup waveforms from off-state at various input voltages. note that there is a fixed startup delay of ~70 s before switching starts. subsequent rise time of the led current depends on input/output voltages, inductor value, and switching frequency . ? operating conditions: led voltage = 3.5 v , led current = 1.5 a, r 1 = 73.2 k (frequency = 1 mhz in steady state), l1 = 15 h, v in = 7 v (panel 1a), 12 v (panel 1b), and 18 v (panel 1c) ? oscilloscope settings: ch1 (red) = v in (5 v/div), ch2 (blue) = v sw (5 v/div), ch3 (green) = i led (500 ma/div), ch4 (yellow) = enable (5 v/div), time scale = 20 s/div c1,c2 c3 c4 automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 figure 2: pwm operation at various duty cycles; note that there is no startup delay during pwm dimming operation ? operating conditions: pwm dimming at 200 hz, v in = 12 v, v out = 7 v, r1 = 73.2 k, duty cycle = 50% (panel 2a) and 2% (panel 2b) ? ch1 (red) = v in (5 v/div), ch2 (blue) = v out (5 v/div), ch3 (green) = i led (500 ma/div), ch4 (yellow) = enable (5 v/div), time scale = 1 ms/div (panel 2a) and 50 s/div (panel 2b) panel 2a. duty cycle = 50% and time scale = 1 ms/div panel 2b. duty cycle = 2% and time scale = 50 s/div c1,c2 c3 c4 automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 0.001 0.01 0.1 1 0.1 1 10 100 normalize led current pwm dimming duty cycle (%) v in = 24 v, load = 2 led v in = 12 v, load = 1 led v in = 12 v, load = 2 led ideal figure 3: efficiency versus led current at various led voltages operating conditions: f sw = 1 mhz figure 4: efficiency versus led current at various switching frequencies. operating conditions: v in = 12 v, v out = 5.5 v figure 5. average led current versus pwm dimming percentage operating conditions: v in = 12 or 24 v, v out = 3.7 v (1 led) or 7 v (2 led), i led = 1.5 a, r on = 73.2 k, f sw = 1 mhz, l = 15 h 95 90 85 80 75 70 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency, (%) led current, i led (a) v in = 24 v, v out = 15 v v in = 12 v, v out = 5.5 v v in = 12 v, v out = 3.5 v 95 90 85 80 75 70 0 0.5 1.0 1.5 2.0 2.5 3.0 efficiency, (%) led current, i led (a) f sw = 500 khz f sw = 1 mhz f sw = 2 mhz automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 the A6217 is a buck regulator designed for driving a high-current led string. it uses average current mode control to maintain constant led current and consistent brightness. the led current level is easily programmable by selection of an external sense resistor, with a value determined as follows: i led = v csreg / r sense where v csreg = 0.2 v typical. switching frequency the A6217 operates in fixed on-time mode during switching. the on-time (and hence switching frequency) is programmed using an external resistor connected between the vin and ton pins, as given by the following equations: t on = k (r on + r int ) ( v out / v in ) f sw = 1 / [ k (r on + r int )] + c where k = 0.014 and c = 0.09, with f sw in mhz, t on in s, and r on and r int (internal resistance, 6 k) in k (see figure 6). to minimize the peaks of switching frequency harmonics in emc measurement, a dithering feature is implemented. the dithering range is internally set at 5%. the actual switching frequency is swept linearly between 0.95 f sw and 1.05 f sw , where f sw is the programmed switching frequency. the rate of modulation for f sw is fixed internally at ~11 khz. enable and dimming the ic is activated when a logic high signal is applied to the en (enable) pin. the buck converter ramps up the led current to a tar get level set by rsense. when the en pin is forced from high to low, the buck converter is turned off, but the ic remains in standby mode for up to 12 ms. if en goes high again within this period, the led current is turned on immediately. active dimming of the led is achieved by sending a pwm (pulse-width modulation) signal to the en pin. the resulting led brightness is proportional to the duty cycle ( t on / period ) of the pwm signal. a practical range for pwm dim- functional description figure 6: average switching frequency versus r on resistance (v in = 12 v, v out = ~7 v, i led = 1 a) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 f sw (mhz) r on (k ? ) figure 7: simplified buck controller equations during sw on-time: i ripple = [( v in ? v out ) / l] t on = [( v in ? v out ) / l] t sw d i ripple = [( v out ? v d ) / l] t off = [( v out ? v d ) / l] t sw (1 ? d) v out = v in d ? v d (1 ? d) v out = ( v in ? i av r ds(on) ) d ? v d (1 ? d) ? r l i av where d = t on / t sw . during sw off-time : therefore (simplified equation for output voltage): more precisely: where r l is the resistance fo the inductor . if v d << v out , then v out v in d. v sw i l t t v in i(max ) i av i(min) 0 i rippl e t on t of f t sw ?v d c in vin A6217 sw v out r sense l i l mos d automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 figure 8: minimum and maximum output voltage versus switching frequency (v in = 16 v, i led = 1 a, minimum t on = 100 ns and t off = 150 ns) figure 9: minimum and maximum output voltage versus i led current (v in = 9 v, f sw = 1 mhz, minimum t on = 100 ns and t off = 150 ns) ming frequency is between 100 hz (period = 10 ms) and 2 khz. at a 200 hz pwm frequency , the dimming duty cycle can be varied from 100% down to 1% or lower. if en is low for more than 20 ms, the ic enters shutdown mode to reduce power consumption. the next high signal on en will initialize a full startup sequence, which includes a startup delay of approximately 70 s. this startup delay is not present during pwm operation. the en pin is high-voltage tolerant and can be directly connected to a power supply . however , if en is higher than the v in voltage at any time, a series resistor (1 k) is required to limit the current flowing into the en pin. this series resistor is not necessary if en is driven from a logic input. pwm dimming ratio the brightness of the led string can be reduced by adjusting the pwm duty cycle at the en pin as follows: dimming ratio = pwm on-time / pwm period for example, by selecting a pwm period of 5 ms (200 hz pwm frequency) and a pwm on-time of 50 s, a dimming ratio of 1% can be achieved. in an actual application, the minimum dimming ratio is deter - mined by various system parameters, including: v in , v out , inductance, led current, switching frequency, and pwm frequency. as a general guideline, the minimum pwm on-time should be kept at 50 s or longer . a shorter pwm on-time is acceptable under more favorable operating conditions. output voltage and duty cycle figure 7 provides simplified equations for approximating output voltage. essentially, the output voltage of a buck converter is approximately given as: v out = v in d C v d1 (1 C d ) v in d, if v d1 << v out d = t on / (t on + t off ) where d is the duty cycle, and v d1 is the forward drop of the schottky diode d1 (typically under 0.5 v). minimum and maximum output voltages for a given input voltage, the maximum output voltage depends on the switching frequency and minimum t off . for example, if t off (min) = 150 ns and f sw = 1 mhz, then the maximum duty cycle is 85%. so for a 24 v input, the maximum output is 20.3 v. this means up to 6 leds can be operated in series, assuming v f = 3.3 v or less for each led. the minimum output voltage depends on minimum t on and switching frequency. for example, if the minimum t on = 100 ns and f sw = 1 mhz, then the minimum duty cycle is 10%. that means with v in = 24 v, the minimum v out = 2.4 v (one led). t o a lesser degree, the output voltage is also affected by other factors such as led current, on-resistance of the high-side switch, dcr of the inductor, and forward drop of the low-side diode. the more precise equation is shown in figure 7. as a general rule, switching at lower frequencies allows a wider range of v out , and hence more flexible led configurations. this is shown in figure 8. figure 9 shows how the minimum and maximum output volt- 0 2 4 6 8 10 12 14 16 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v out (v) frequency (mhz) v out (max) (v) v out (min) (v) 0 1 2 3 4 5 6 7 8 9 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 v out (v) i led (a) v out (max) (v) v out (min) (v) automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 ages vary with led current (assuming r ds(on) = 0.4 , inductor dcr = 0.1 , and diode v f = 0.6 v). if the required output voltage is lower than that permitted by the minimum t on , the controller will automatically extend the t off , in order to maintain the correct duty cycle. this means that the switching frequency will drop lower when necessary , while the led current is kept in regulation at all times. fault handling the A6217 is designed to handle the following faults: ? pin-to-ground short ? pin-to-neighboring pin short ? pin open ? external component open or short ? output short to gnd the waveform in figure 10 illustrates how the A6217 responds in the case in which the current sense resistor or the cs pin is shorted to gnd. note that the sw pin overcurrent protection is tripped at around 4.2 a, and the part shuts down immediately. the part then goes through startup retry after approximately 360 s of cool-down period. figure 11: startup waveform with a missing schottky diode; shows enable, v en (ch1, 5 v/div.), switch node, v sw (ch2, 5 v/div.), output voltage, v out (ch3, 5 v/div.), led current, i led (ch4, 500 ma/div.), t = 100 s/div. t c1 c3 c4 c2 v sw v en negative voltage developed at sw pin during off-time v out i led figure 10: A6217 during fault condition where the sense resistor or cs pin is shorted to gnd. ch1 = vout (5 v/div), ch2 = i_led (500 ma/div), t = 200 s/div. A6217 tripped sw_ilim at ~4.2 a cooldown period ~ 360 s i_led vout sense resistor shorted during normal operation c1 c2 t automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 as another example, the waveform in figure 11 shows the fault case where external schottky diode d1 is missing or open. as led current builds up, a larger-than-normal negative voltage is developed at the sw node during off-time. this voltage trips the missing schottky detection function of the ic. the ic then shuts down immediately, and waits for a cool-down period before retry. component selections the inductor is often the most critical component in a buck con- verter. follow the procedure below to derive the correct param- eters for the inductor: 1. determine the saturation current of the inductor. this can be done by simply adding 20% to the average led current: i sat i led 1.2. 2. determine the ripple current amplitude (peak-to-peak value). as a general rule, ripple current should be kept between 10% and 30% of the average led current: 0.1 < i ripple(pk-pk) / i led < 0.3. 3. calculate the inductance based on the following equations: l = (v in C v out ) d t / i ripple , and d = (v out + v d1 ) / ( v in + v d1 ) , where d is the duty cycle, t is the period 1/ f sw , and v in sw d1 led+ led? l1 cs . . . i ripple v ripple v ripple r sense v in sw d1 led+ led? l1 cs c1 . . . i ripple r sense figure 13. ripple current and voltage, with and without shunt capacitor without output capacitor: ripple current through led string is proportional to ripple voltage at cs pin. with a small capacitor across led string: ripple current through led string is reduced, while ripple voltage at cs pin remains high. figure 12: inductance selection based on i led and f sw ; v in = 12 v, v out = 6 v, ripple current = 20% 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.5 1 1.5 2 switching frequency (mhz) led current (a) l = 10 h l = 15 h l = 22 h l = 33 h l = 47 h v d1 is the forward voltage drop of the schottky diode d1 (see figure 7). inductor selection chart the chart in figure 12 summarizes the relationship between led current, switching frequency, and inductor value. based on automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 figure 14: waveforms showing the effects of adding a small filter capacitor across the led string ? operating conditions: at 200 hz, v in = 24 v, v out = 15 v, f sw = 500 khz, l = 10 h, duty cycle = 50% ? ch1 (red) = v in (10 v/div), ch2 (blue) = v out (10 v/div), ch3 (green) = i led (500 ma/div), ch4 (yellow) = enable (5 v/div), time scale = 1 ms/div panel 14a: operation without using any output capacitor across the led string panel 14b: operation with a 0.68 f ceramic capacitor connected across the led string t c1,c2 c3 c4 v in v out i led v en t c1,c2 c3 c4 v in v out i led v en this chart: assuming led current = 1 a and f sw =1 mhz, then the minimum inductance required is l = 22 h in order to keep the ripple current at 30% or lower. (note: v out = v in / 2 is the worst case for ripple current). if the switching frequency is lower, then either a larger inductance must be used, or the ripple current requirement has to be relaxed. additional notes on ripple current ? for consistent switching frequency, it is recommended to choose the inductor and switching frequency to ensure the induc- tor ripple current percentage is at least 10% over normal operat- ing voltage range (ripple current is lowest at lowest v in ). if ripple current is less than 10%, the switching frequency may jitter due to insuf ficient ripple voltage at cs pin. however , the average led current is still regulated. ? there is no hard limit on the highest ripple current percentage allowed. a 60% ripple current is still acceptable, as long as both the inductor and leds can handle the peak current (average cur- rent 1.3 in this case). however , care must be taken to ensure the valley of the inductor ripple current never drops to zero at the highest input voltage (which implies a 200% ripple current). ? in general, allowing a higher ripple current percentage enables lower-inductance inductors to be used, which results in smaller size and lower cost. the only downside is the core loss of the inductor increases with larger ripple currents, but this is typically a small factor . ? if lower ripple current is required for the led string, one solu- tion is to add a small capacitor (such as 2.2 f) across the led string from led+ to ledC . in this case, the inductor ripple cur- rent remains high while the led ripple current is greatly reduced. output filter capacitor the A6217 is designed to operate without an output filter capaci - tor, in order to save cost. adding a large output capacitor is not recommended. in some applications, it may be required to add a small filter capacitor (up to several f) across the led string (between led+ and ledC) to reduce output ripple voltage and current. it is important to note that: ? the effectiveness of this filter capacitor depends on many fac- tors, such as: switching frequency, inductors used, pcb layout, led voltage and current, and so forth. ? the addition of this filter capacitor introduces a longer delay in led current during pwm dimming operation. therefore the maximum pwm dimming ratio is reduced. ? the filter capacitor should not be connected between led+ and gnd. doing so may create instability because the control loop must detect a certain amount of ripple current at the cs pin for regulation. automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 application circuit the application circuit in figure 15 shows a design for driving a 15 v led string at 1.3 a (set by r sense ). the switching fre- quency is 500 khz, as set by r1. a 0.68 f ceramic capacitor is added across the led string to reduce the ripple current through the leds (as shown in figure 14b). figure 15: application circuit diagram suggested components symbol part number manufacturer c1 emza500ada470mf80g united chemi-con c2 umk316bj475kl-t taiyo yuden c3 cga5l2x5r1h684k160aa tdk l1 nr8040t100m taiyo yuden d1 b250a-13-f diodes, inc. r sense rl1632r-r150-f susumu figure 16: pwm dimming of led current by using pulsed power supply line additional application circuits the following are some application examples to expand the capa- bility of the A6217: ? figure 16 shows pwm dimming of led current by pulsing the power supply line ? figure 17 shows analog dimming of led current by an exter- nal dc voltage ? figure 18 shows thermal de-rating of led current by an ntc resistor led+ led? vin ton en cs sw boot gnd vcc A6217 (ej) 1, 2 3 4 5 9,10 8 7 6 v in = 24 to 48 v c1 4 7 f 5 0 v c2 4.7f 50v en c4 0.1 f r1 169 k l1 10 h / 2 a c5 0.1 f r sense 0.15 gnd d1 60 v / 2 a c3 0.6 8 f 5 0 v led string ( 15 v) ... pad vbat gnd vin 10 k vbat 12 v 0 led current 1 a 0 vba t pulsed on/o ff at 200 hz, with duty cycle between 1 % and 99% 1, 2 3 4 5 vin to n en cs sw boot gnd vcc 9,10 8 7 6 A6217 (ej) led+ led? led string (~6 v) r sense 0.2 automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
14 figure 17: analog dimming of led current with an external dc voltage figure 18: thermal foldback of led current using ntc resistor v in = 12 v gnd 200 k 25 k 1 k 1, 2 3 4 5 vin to n en en cs sw boot gnd vcc 9,10 8 7 6 A6217 (ej) led+ ledC led string (~6 v) r sense 0.2 r1 c1 47 f 50 v c2 4.7 f 50 v c4 0.1 f c5 0.1 f v cs = 0.2 v adim adim i adim analog dimming vo ltage: 0 to 5.2 v d1 60 v 2 a c3 open l1 47 h 2 a v sense : 0.22 v to 0 v i led : 1.04 a to 0 a i led i led = (0.2 v C i adim 1000)/r sense i adim = (v adim C 0.2)/25 k 100% 0 0.2 v5 .2 v gnd 200 k 30 k 1 k 1, 2 3 4 5 vin to n en cs sw boot gnd vcc 9,10 8 7 6 A6217 (ej) led+ ledC led string (~6 v) r sense 0.2 r1 c1 47 f 50 v c2 4.7 f 50 v c4 0.1 f c5 0.1 f v cs = 0.2 v v cc = 5.2 v i adim : 0.02 ma @ 25oc 0.096 ma @ 100oc ntc: 220 k @ 25oc 22 k @ 100oc d1 60 v 2 a c3 open l1 47 h 2 a v sense : 0.18 v @ 25oc 0.104 v @ 100oc i led = (0.2 v C i adim 1000)/r sense i adim = (v cc C 0.2)/(r ntc + 30 k) 0.9 a @ 25oc 0.52 a @ 100oc automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
15 component placement and pcb layout guidelines pcb layout is critical in designing any switching regulator. a good layout reduces emitted noise from the switching device, and ensures better thermal performance and higher efficiency. the following guidelines help to obtain a high quality pcb layout. figure 19 shows an example for components placement. figure 20 shows the three critical current loops that should be minimized and connected by relatively wide traces. 1) when the upper fet (integrated inside the A6217) is on, cur- rent flows from the input supply/capacitors, through the upper fet, into the load via the output inductor, and back to ground as shown in loop 1. this loop should have relatively wide traces. ideally this connection is made on both the top (component) layer and via the ground plane. 2) when the upper fet is off, free-wheeling current flows from ground through the asynchronous diode d1, into the load via the output inductor, and back to ground as shown in loop 2. this loop should also be minimized and have relatively wide traces. ideally this connection is made on both the top (component) layer and via the ground plane. 3) the highest di/dt occurs at the instant the upper fet turns on and the asynchronous diode d1 undergoes reverse recovery as shown in loop 3. the ceramic input capacitors c2 must deliver this high instantaneous current. c1 (electrolytic capacitor) should not be too far off c2. therefore, the loop from the ceramic input capacitor through the upper fet and asynchronous diode to ground should be minimized. ideally this connection is made on both the top (component) layer and via the ground plane. 4) the voltage on the sw node (pin 8) transitions from 0 v to v in very quickly and may cause noise issues. it is best to place the asynchronous diode and output inductor close to the A6217 to minimize the size of the sw polygon. keep sensitive analog signals (cs, and r1 of switching fre - quency setting) away from the sw polygon. 6) for accurate current sensing, the led current sense resistor r sense should be placed close to the ic. 7) place the bootstrap capacitor c4 near the boot node (pin 7) and keep the routing to this capacitor short. 8) when routing the input and output capacitors (c1, c2, and c3 if used), use multiple vias to the ground plane and place the vias as close as possible to the A6217 pads. 9) to minimize pcb losses and improve system ef ficiency, the input (vin) and output (vout) traces should be wide and dupli- cated on multiple layers, if possible. figure 20: three different current loops in a buck converter figure 19: example layout for the A6217 evaluation board (package lj) v in c in c out d1 l1 led sw loop 2 loop 1 loop 3 automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
16 10) connection to the led array should be kept short. exces- sively long wires can cause ringing or oscillation. when the led array is separated from the converter board and an output capaci- tor is used, the capacitor should be placed on the converter board to reduce the effect of stray inductance from long wires. ?0.3 mm via top-layer exposed copper signal traces lj package exposed thermal pad lj package footprint 0.7 mm 0.7 mm figure 21: suggested pcb layout for thermal optimization (maximum available bottom-layer copper recommended) thermal dissipation the amount of heat that can pass from the silicon of the A6217 to the surrounding ambient environment depends on the thermal resistance of the structures connected to the A6217. the thermal resistance, r ja , is a measure of the temperature rise created by power dissipation and is usually measured in degrees celsius per watt (c/w). the temperature rise, t, is calculated from the power dissipated, p d , and the thermal resistance, r ja , as: t = p d r ja a thermal resistance from silicon to ambient, r ja , of approxi- mately 35c/w (lj package) or 45c/w (ej package) can be achieved by mounting the A6217 on a standard fr4 double-sided printed circuit board (pcb) with a copper area of a few square inches on each side of the board under the A6217. additional improvements in the range of 20% may be achieved by optimiz - ing the pcb design. optimizing thermal layout the features of the printed circuit board, including heat conduc - tion and adjacent thermal sources such as other components, have a very significant effect on the thermal performance of the device. to optimize thermal performance, the following should be taken into account: ? the device exposed thermal pad should be connected to as much copper area as is available. ? copper thickness should be as high as possible (for example, 2 oz. or greater for higher power applications). ? the greater the quantity of thermal vias, the better the dissipa - tion. if the expense of vias is a concern, studies have shown that concentrating the vias directly under the device in a tight pattern, as shown in figure 21, has the greatest effect. ? additional exposed copper area on the opposite side of the board should be connected by means of the thermal vias. the copper should cover as much area as possible. ? other thermal sources should be placed as remote from the device as possible ? place as many vias as possible to the ground plane around the anode of the asynchronous diode. automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
17 package outline drawings package ej, 10-pin dfn with exposed thermal pad and wettable flank for reference only ?n ot for tooling use (reference jedec mo-229) dimensions in millimeters ? not to scale exact case and lead con?guration at supplier discretion within limits shown 10 10 2 1 2 1 a a b d c b 1.64 2.38 0.30 1 10 0.50 0.85 3.10 c c 0.05 10 x c seating plane d 0.25 0.05 0.05 0.00 2.38 0.10 1.65 0.10 0.5 bsc 0.75 0.05 3.00 0.05 3.00 0.05 0.40 0.10 pcb layout reference vi ew terminal #1 mark area exposed thermal pad (reference onl y, terminal #1 identi?er appearance at supplier discretion) coplanarity includes exposed thermal pad and terminals reference land pattern layout (reference ipc7351 son50p300x300x80-11weed3m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) 0.05 ref 0.40 0.10 0.05 ref 0.08 ref 0.203 ref detail a detail a automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
18 package lj, 8-pin soicn with exposed thermal pad 3.30 2 1 8 c 1.27 5.60 2.41 1.75 0.65 2.41 nom 3.30 nom seating plane 1.27 bsc a b c b 21 8 c seating plane c 0.10 8x 0.25 bsc 1.04 ref 1.70 max 4.90 0.10 3.90 0.10 6.00 0.20 0.51 0.31 0.15 0.00 0.25 0.17 1.27 0.40 8 0 a branded face for reference only; not for tooling use (reference ms-012ba) dimensions in millimeters dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown terminal #1 mark area exposed thermal pad (bottom surface); dimensions may vary with device reference land pattern layout (reference ipc7351 soic127p600x175-9am); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view seating plane gauge plane automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
19 for the latest version of this document, visit our website: www.allegromicro.com revision history number date description C august 8, 2016 initial release copyright ?2016, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. automotive-grade, constant-current pwm dimmable buck regulator led driver A6217 and A6217-1 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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